The present invention concerns placing circuits designs onto semiconductor chips. In particular, the present invention involves an improved method of using field-programmable gate arrays.
Currently, two common systems are used for implementing circuits on semiconductor chips. The first system uses mask-programmable gate arrays. In mask-programmable gate arrays, the circuit design is used to produce process masks that are used for the formation of chips. The masks, and thus the chip fabrication system, can only produce a single circuit. The mask-programmable gate array is optimized for this circuit, so this mask-programmable gate array can have a relatively small area and a high speed. Additionally, the mask-programmable gate arrays have good unit costs per chip for high-volume production of semiconductor chips.
The second system of implementing circuits on semiconductor chips uses field-programmable gate arrays. Field-programmable gate arrays are described in a special issue of Proceedings of the IEEE, Volume 81, No. 7, July 1993, which is incorporated herein by reference. Field-programmable gate arrays (FPGAs) are recently-developed electronically programmable integrated circuits. The benefit of FPGAs is that a single FPGA design can be used for implementing many circuit designs. The FPGA chips have good low-volume production costs because of the low overhead costs associated with programming the chip. FPGAs, however, are slower and have a relatively large area compared to mask-programmable chips containing a circuit of the same logic capacity. The slowness of FPGAs is generally a result of the signal paths routed through the programmable interconnect structures on the FPGA. The larger area of FPGAs is a result of the additional overhead on the chip used for programmable interconnect structures (switches with associated static memory, anti-fuses, or floating gate transistors), control logic, and under-utilized logic blocks or interconnect structures.
It is desired to have a system for implementing circuits with improved speed and/or smaller area than in previous systems for implementing a circuit onto an FPGA.